Epoxy EP112 Used in Microelectronics Fabrication

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Master Bond EP112 is an ultra-low-viscosity, electrically insulating, two-component warmth curable epoxy system designed for demanding purposes requiring optical readability and resistance to chemical compounds generally utilized in silicon processing. This text introduces a two-part case examine involving a microelectronics fabrication, showcasing EP112’s position in bonding a silicon wafer to a glass substrate.

Half 1: The START Course of and EP112’s Function

Within the first a part of this case examine, researchers at Lawrence Livermore Nationwide Laboratory (LLNL) developed an progressive Silicon-on-Insulator (SOI) course of referred to as START (Silicon Switch to Arbitrary Substrate). This methodology allows the transformation of normal bulk silicon wafers with accomplished circuits into SOI-like configurations with out considerably rising manufacturing prices. Through the use of standard fabrication strategies, the START course of combines the advantages of bulk silicon electronics with these of SOI know-how whereas sustaining value effectivity.

A essential step on this course of concerned bonding a silicon wafer to a glass help substrate. EP112 was chosen because the adhesive of alternative as a consequence of its ultra-low viscosity, sturdy bonding capabilities, and excessive chemical resistance. The bonded construction in the end contributed to the profitable growth of a prototype liquid crystal show (LCD), demonstrating EP112’s effectiveness in microelectronics fabrication.

Half 2: CMOS Wafer Thinning for SEU Resistance

Within the second a part of this examine, LLNL researchers utilized EP112 in a novel wafer-thinning course of to boost the reliability of CMOS-based built-in circuits (ICs). The target was to cut back susceptibility to Single Occasion Upsets (SEUs) by considerably lowering the cost assortment quantity throughout the silicon substrate.

To attain this, EP112 was used to bond two substrates collectively, guaranteeing a safe attachment all through the wafer-thinning steps. The method concerned a high-temperature alkaline etching step, the place EP112’s superior chemical resistance performed a vital position in stopping de-bonding. By sustaining structural integrity beneath these harsh circumstances, EP112 enabled the profitable completion of the thinning course of, additional demonstrating its suitability for superior semiconductor purposes.

To learn extra about the important thing parameters and necessities, and be taught in regards to the outcomes, please download the full case study here.